test if a type can be vectorized

[Matthias Kretz]

On Freitag, 29. September 2017 14:49:19 CEST nicholas ferguson wrote:
> It would say it's easier to answer if you stated your algorithm. Since SIMD
> is single instruction multiple data.... what algorithm requires that?

Such a trait is useful in generic code. You can dispatch to different code, 
depending on whether instantiation of Vector<T> (or simd<T> in current master) 
would be ill-formed or valid. Thus, automatically vectorize whenever Vc 
supports it. And, if a newer release supports more types, it just works.

Cheers,
  Matthias


> -----Original Message-----
>[please enable javascript to see the address]
>[please enable javascript to see the address]] On Behalf Of Kay F. Jahnke
> Sent: Friday, September 29, 2017 2:25 AM
>[please enable javascript to see the address]
> Subject: test if a type can be vectorized
> 
> Dear group!
> 
> I'd like to perform a test on some type T which tells me whether Vc can form
> a Vc::Vector from it. I'd like something like
> 
> is_simdizable<T>::value
> 
> to yield true if Vc::Vector<T> can be formed, false otherwise, so that I can
> use the result to dispatch to fall-back code if there is no Vc:Vector<T>.
> 
> Help appreciated.
> 
> With regards
> 
> Kay F. Jahnke
> 
> 
> .
> 
> _______________________________________________
> Vc mailing list
>[please enable javascript to see the address]
> https://compeng.uni-frankfurt.de/mailman/listinfo/vc
> 
> 
> 
> _______________________________________________
> Vc mailing list
>[please enable javascript to see the address]
> https://compeng.uni-frankfurt.de/mailman/listinfo/vc


-- 
──────────────────────────────────────────────────────────────────────────
 Dr. Matthias Kretz                                https://kretzfamily.de
 GSI Helmholtzzentrum für Schwerionenforschung             https://gsi.de
 SIMD easy and portable                     https://github.com/VcDevel/Vc
──────────────────────────────────────────────────────────────────────────